Design and FPGA Implementation of Integer Transform and Quantization Processor and Their Inverses for H.264 Video Encoder

This paper proposes a novel implementation of the core processors, intra prediction, the integer transform, quantization, inverse quantization and inverse transformation for H.264 Video Encoder using an FPGA. It is capable of processing video frames with the desired compression controlled by the user input. The algorithm and architecture of the core modules of the video encoder namely, horizontal mode of intra prediction, the integer transform, quantization, inverse quantization and inverse transformation were developed, designed and coded in Verilog. The complete H.264 Advanced Video Codec was coded in Matlab in order to verify the results of the Verilog implementation. The processor is implemented on a Xilinx Vertex–II Pro XUPVP30 FPGA. The gate count of the implementation is approximately 870,000. It can process 1024x768 pixels moving color pictures in 4:2:0 format at 25 frames per second. The reconstructed picture quality is better than 35 dB.